Crosstalk simulation analysis between high speed differential vias

In hardware system design, the primary concern regarding crosstalk typically involves signals passing through connectors, chip packages, and closely spaced parallel traces. However, in certain high-speed designs, significant crosstalk can also occur between differential vias. This paper presents a case study involving simulation and analysis of crosstalk specifically between high-speed differential vias, offering insights into how to address this issue effectively. **Crosstalk Between High-Speed Differential Vias** For thicker PCBs, such as those with a thickness of 2.4mm or 3mm, the length of a through-hole in the Z-direction can be quite longâ€”up to nearly 118 mils in the case of a 3mm board. When paired with a BGA component that has a 0.8mm pitch, the fan-out via spacing may only be around 31.5 mils. This close proximity increases the likelihood of crosstalk, especially when multiple differential vias are placed in close proximity. As shown in Figure 1, the parallel length (H) of two adjacent differential via pairs along the Z-axis is greater than 100 mils, while the horizontal spacing (S) between these vias is only 31.5 mils. In such configurations, where the Z-direction spacing is significantly larger than the horizontal spacing, crosstalk between high-speed differential vias becomes a critical concern. It's important to note that in high-speed PCB design, minimizing via stub length is essential to reduce signal degradation. As illustrated, the stub length on the bottom layer is shorter, or alternatively, back-drilling techniques can be employed to further reduce this impact.

Figure 1: High-speed differential vias for crosstalk (H > 100mil, S = 31.5mil)
**Simulation Analysis of Crosstalk Between Differential Vias** The following simulation example involves a 3mm thick PCB, a BGA with a 0.8mm pitch, resulting in a fan-out via spacing of 31.5 mils, and a via parallel length of H = 112 mils. As shown in Figure 2, we defined four pairs of differential pairs, converting them into eight differential ports based on the trace layout.

Figure 2: Crosstalk simulation port definition
Assuming that D1â€“D4 are the receiving ends of the chip, we analyzed the crosstalk between adjacent channels by examining the far-end crosstalk at D5, D7, and D8 from the D2 ports. The results in Figure 3 show that crosstalk between adjacent channels can reach -37dB at 5GHz and -32dB at 10GHz, indicating that further optimization is necessary to minimize this effect.

Figure 3: Crosstalk simulation results between differential pairs
You might wonder how we differentiate crosstalk caused by differential vias from that caused by differential traces. To clarify this, we divided the example into two parts: the BGA fan-out area and the differential trace section. The simulation results are shown in Figure 4:

Figure 4: BGA fan-out area and differential trace crosstalk simulation results
From the right side of Figure 4, it's clear that the crosstalk between differential traces is well below -50dB, even reaching -60dB in the 10GHz range. Meanwhile, the crosstalk in the BGA fan-out area closely matches the overall simulation result. Based on these findings, we can conclude that crosstalk between differential vias is the dominant factor in this example.
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