Crosstalk simulation analysis between high speed differential vias

In hardware system design, the primary concern regarding crosstalk typically revolves around signals passing through connectors, chip packages, and parallel traces that are closely spaced. However, in high-speed PCB designs, especially those involving complex BGA (Ball Grid Array) layouts, significant crosstalk can also occur between high-speed differential vias. This paper presents a practical simulation analysis along with solutions aimed at mitigating crosstalk between these critical components. **Crosstalk Between High-Speed Differential Vias** For thicker PCBs, such as those with a thickness of 2.4mm or 3mm, the length of a via extending through the board in the Z-direction can be quite substantial. For example, on a 3mm thick board, the via length can reach nearly 118 mils. When paired with a BGA component having a pitch of 0.8mm, the fan-out via spacing is often limited to approximately 31.5 mils, which significantly increases the potential for crosstalk. As illustrated in Figure 1, when two pairs of adjacent differential vias have a parallel length (H) exceeding 100 mils in the Z-direction, and their horizontal spacing (S) is only 31.5 mils, the risk of crosstalk becomes more pronounced. In high-speed PCB design, it's crucial to minimize the length of via stubs to reduce signal degradation. As shown in the figure, the stub length on the bottom layer is shorter, or alternatively, back-drilling techniques can be employed to further reduce this effect.

Figure 1: High-speed differential vias for crosstalk (H > 100mil, S = 31.5mil)
**Simulation Analysis of Crosstalk Between Differential Vias** This section presents a simulation based on a design featuring a 3mm thick PCB, a 0.8mm BGA with a fan-out pitch of 31.5 mils, and a via parallel distance of H = 112 mils. As shown in Figure 2, we define four pairs of differential signals into eight differential ports based on the trace layout.

Figure 2: Crosstalk simulation port definition
Assuming that D1â€“D4 represent the receiving ports of the chip, we analyze the crosstalk between adjacent channels by observing the far-end crosstalk from the D2 ports onto D5, D7, and D8. The results in Figure 3 show that the far-end crosstalk between closely spaced channels can reach -37dB at 5GHz and -32dB at 10GHz. These values indicate that further optimization is necessary to achieve better performance.

Figure 3: Crosstalk simulation results between differential pairs
You may wonder: How can we distinguish crosstalk caused by differential vias from that caused by differential traces? To address this, we split the original example into two parts: the BGA fan-out area and the differential trace section. The simulation results are presented in Figure 4:

Figure 4: BGA fan-out area and differential trace crosstalk simulation results
From the right side of Figure 4, itâ€™s clear that the crosstalk between differential traces is well below -50dB, even reaching -60dB in the 10GHz range. Meanwhile, the crosstalk in the BGA fan-out area closely matches the overall simulation result. Based on this, we can conclude that the crosstalk observed in the original example is primarily due to the differential vias, not the differential traces.
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