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A brief introduction to how to write code and generate download files
When remotely upgrading the FPGA code of a product, it's common practice to send an encrypted download file to the user, allowing them to perform the update locally. However, there are instances where mistakes occur during the process—such as errors in the update program—that can lead to unexpected behavior or even system failure after the upgrade. If the issue isn't urgent, communication with the user and re-sending the corrected file is usually sufficient. But for equipment that operates continuously without interruption, any delay in resolving the problem can result in significant downtime and operational challenges.
To avoid such issues, it’s highly recommended to implement multiple configuration functions when performing remote FPGA upgrades. This approach allows the system to fall back on a previous, stable configuration if the new one fails, ensuring uninterrupted operation.
1. **ICAPE Core**
The ICAPE core is essential when using multiple configuration features within the FPGA. It enables the execution of IPROG instructions, which are used to load different configurations dynamically. To access the ICAPE core, you can search for "ICAPE" in the "Language Templates" section of Vivado, or use similar tools in ISE. This core acts as a bridge between the Flash memory and the FPGA, managing the configuration switching process.
2. **Multiple Configuration Code**
The multi-configuration code is stored alongside the original program in Flash memory. Typically, the old program starts at address 0x0, while the updated version is placed afterward. Upon power-up, the FPGA reads from the beginning of the Flash and checks the ICAPE core in the original program to decide whether to load the new configuration. This setup ensures that if the update fails, the system can automatically revert to the previous, working version.
3. **Packaging Multiple Configuration Files**
In Vivado, when generating an .xdc file, it's important to include information about how the Flash memory will be used. For example, you need to set the Flash device to SPI mode and configure the read/write speed accordingly. After generating both the old and new .bit files, they are merged into a single .mcs file using the "Generate Memory Configuration File" option under the Tools menu. This process ensures that the Flash contains all necessary data for both configurations.
Once the .mcs file is created, it can be sent to the user. If the new configuration fails during loading, the FPGA will automatically switch back to the previous version, maintaining system stability. Additionally, users can enhance this functionality by adding control signals—such as a physical button—to manually trigger the reload of the new configuration. This provides more flexibility and control over the update process.
By implementing these steps, developers can significantly reduce the risk of system failures due to faulty updates, making remote FPGA upgrades more reliable and efficient.
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