Research and Implementation of UAV Flight Control System Based on ARM

I. Introduction

The UAV flight control system is a comprehensive system with high-performance autonomous navigation, automatic flight control, and task management. It requires a lot of complicated data processing and mathematical operations. The flight control computer is the core subsystem of the flight control system. With the development of aerospace technology, the flight control computer is developing in the direction of high precision and miniaturization. The high precision requires the guidance control of the UAV to have high precision and good stability, and can adapt to the complicated external environment, resulting in a complicated control algorithm, high calculation speed and high precision. Miniaturization puts higher demands on the weight and volume of the control system. The higher the performance of the computer, the better the smaller the size. Performance indicators and volume constraints urgently require the development of new flight control computers.

Second, the flight control computer and peripheral interface design requirements

The key to the design of the ARM-based flight control computer is the overall system design. Interface design is an important link. Its quality will directly affect the performance of the system. The signal input and output should be considered anti-interference. The overall design should be easy to implement, and it must have certain adaptability to different types of drones. For models with similar requirements, it is better to modify the control software, with little or no change to the hardware design. These requirements must be considered in all aspects of the design.

First of all, the demand analysis of the flight control/navigation task and the achievement target of the drone is required. According to the flight requirements and the complexity of the control object, the control cycle is selected; the type of calculation and the calculation speed are determined according to the control calculation amount in the control cycle, and the interface scheme is determined in combination with the external unit, and the consideration of the countermeasure against interference factors can determine the overall communication. Protocol and interface form.

In the flight process of the drone, in order to achieve a certain flight mission, it is necessary to control its flight attitude and guide the aircraft to fly accurately according to a certain route. In order to perform attitude control, it is necessary to obtain real-time parameter information of the flight attitude and remote telemetry parameters. With these information parameters, the computer control algorithm calculates and real-time output control grain to the actuator to achieve control/navigation purposes. The schematic diagram of the structure is shown in Figure 1.

The vertical gyro and triaxial angular rate gyro output are analog signals, so the flight control computer must have high-precision acquisition capability of multiple analog signals. The magnetic heading sensor, height sensor and data exchange with peripheral units such as GPS and remote telemetry use RS-485 and RS-232 communication protocols. Therefore, the flight control computer must have the capacity of multiple serial ports. At the same time, the system requires a series of level output/input interfaces and servos.

1, ARM's choice

From the aspects of calculation accuracy, calculation speed, control performance requirements, power consumption, and the above interfaces, ATMEL's AT91M55800A chip is used as the CPU. The chip integrates the ARM7TDMI core, embedded ICE interface, memory and peripherals.

The AT91M55800A has two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB interface is controlled by the memory control registers for maximum performance. The ARM7TDMI core implements connections to on-chip 32-bit memory, external bus interface (EBI), and AMBA bridges via the ASB interface. The AMBA bridge is used to drive the APB; the APB is used to access the on-chip peripherals to optimize system power consumption. The AT91M55800A connects directly to off-chip memory via a fully programmable external bus interface, allowing read or write operations to be as fast as one clock cycle. 8 priority vector interrupt controllers and on-chip peripheral data controllers significantly improve the real-time performance of the device.

The key features of the AT91M55800A's main hardware resources are as follows:

(1) The chip provides a wealth of on-chip resources. With on-chip A/D and D/A converters, the system eliminates the need for external A/D and D/A chips, which improves system reliability and reduces system complexity. The AT91M55800A has an on-chip watchdog circuit that monitors the program for unexpected loss of control. The AT91M55800A chip provides an SPI bus for easy connection to extended peripherals.

(2) Integrated ARM7TDMIARMThumb processing core - low power and high performance 32-bit RISC (ReducedInstructionSetComputer) processor. Strong command function, it can provide 0.9MIPS/MHz three-stage pipeline and von Neumann structure; it has enhanced multiplier capable of generating 64-bit result; strong addressing capability, ARM instruction set and Thumb instruction set; embedding ICE, advanced software development and debugging environment.

(3) 8KB on-chip SRAM.—32-bit data bus width, single clock cycle access.

(4) Fully Programmable External Bus Interface (EBI)—Maximum addressable space is 64MB, up to 8 chip select lines, software programmable 8-bit or 16-bit external data bus.

(5) 8-priority, individually maskable vectored interrupt controller (AIC)—7 external interrupts, including a high-priority, low-latency interrupt request.

(6) 58 programmable I/O lines, controlled by PIOA and PIOB.

(7) 6-channel 16-bit timer/counter, real-time clock (RTC), system timer, watchdog timer.

(8) Master-slave SPI interface—8~16-bit programmable data length, 4 external slave chips.

(9) Real-time clock using on-chip main oscillator and PLL multiplier clock generator and on-chip 32K oscillator—3MHz~33MHz frequency range.

(10) Has 3 USARTs - each USART has two Peripheral Data Controller (PDC) channels.

(11) 8-channel 10-bit ADC and 2-channel 10-bit DAC.

(12) Advanced Power Management Controller (APMC)—Normal, Waiting, Slow, Standby, and Power Down modes.

(13) JEEE1149.1JTAG boundary scan for all digital pins.

The above functions and features of the AT91M55800A enable complex control algorithms to be completed within a specified time and meet the accuracy requirements.

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