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Keyword identification (KWS) plays a crucial role in enabling voice-based user interaction on smart devices. It requires real-time response and high precision to ensure a seamless user experience. In recent years, neural networks have become a popular choice for KWS due to their superior accuracy compared to traditional speech processing methods.
The keyword identification neural network pipeline is essential for efficient and accurate speech recognition. However, deploying such systems on microcontrollers presents unique challenges.
One of the main limitations of KWS applications is the power budget. Since these systems need to be "always on," they must operate efficiently. While KWS can run on dedicated DSPs or high-performance CPUs, using Arm Cortex-M microcontrollers offers cost-effective and energy-efficient solutions, especially in IoT edge devices that handle multiple tasks.
However, deploying a neural network-based KWS system on a Cortex-M microcontroller comes with several challenges. First, there is limited memory space—typically only a few hundred kilobytes. This means the entire model, including inputs, weights, and activations, must fit within this small memory footprint. Second, computing resources are constrained, and real-time performance requirements limit the number of operations per inference.
Various neural network architectures have been used for KWS, including DNNs, CNNs, RNNs, CRNNs, and DS-CNNs. Each has its own strengths and trade-offs. For example, DNNs are simple but may not capture local correlations in speech data effectively. CNNs, by treating time and frequency features as images, can better model spatial relationships. RNNs excel at capturing temporal dependencies, while CRNNs combine both convolutional and recurrent layers for enhanced performance.
DS-CNNs, or depthwise separable convolutional neural networks, offer a more efficient alternative. They split the standard 3D convolution into two steps: first applying a depthwise convolution on each channel, then a pointwise convolution to merge the results. This reduces the number of parameters and operations, making them ideal for resource-constrained environments like microcontrollers.
When designing a KWS model for Cortex-M processors, memory footprint and execution time are critical factors. Based on typical configurations, three sets of constraints define the limits for small, medium, and large Cortex-M systems.
To meet these constraints, a hyperparameter search is necessary. The table below shows the neural network architectures and their corresponding hyperparameters that must be optimized.
The relationship between memory usage and computational operations in the optimal model is illustrated here. DS-CNNs achieve the highest precision while requiring significantly less memory and computation.
The KWS application was deployed on a Cortex-M7-based STM32F746G-DISCO development board. Using an 8-bit DNN model, it performs 10 inferences per second, with each inference taking about 12 milliseconds. The system uses around 70 KB of memory, with 66 KB allocated for weights, 1 KB for activations, and 2 KB for audio I/O and MFCC features. To save power, the microcontroller can enter WFI mode when idle.
In conclusion, the Arm Cortex-M processor achieves high-accuracy keyword recognition while staying within strict memory and computational limits. The DS-CNN architecture stands out for its efficiency and performance.
Code, model definitions, and pre-trained models are available on GitHub. Our new machine learning developer site provides comprehensive resources, product details, and tutorials to help tackle the challenges of edge AI.
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High precision keyword speech recognition based on Cortex-M processor
We can optimize the neural network architecture to fit within the memory and computational constraints of a microcontroller without sacrificing accuracy. In this paper, we will explore and explain the potential of deep separable convolutional neural networks for implementing keyword recognition on Cortex-M processors.