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Field Effect Transistor (MOSFET) Detection Method and Experience
First, use a pointer multimeter to identify the FET. To determine the electrode of a junction field-effect transistor via the resistance method, you can rely on the fact that the forward and reverse resistances of the PN junction differ. With this approach, you can distinguish the three electrodes of the junction field-effect transistor. Specifically, set the multimeter to the R×1k scale and measure the positive and negative resistance values of two electrodes. If the positive and negative resistance values of a pair of electrodes are equal and several thousand ohms, these two electrodes are the drain D and the source S, respectively. Since the source and drain are interchangeable for the junction field-effect transistor, the remaining electrode must be the gate G. Alternatively, you can touch the black probe (red pen) of the multimeter to one electrode and then contact the remaining two electrodes with the other probe to measure the resistance. When the two measured resistance values are roughly equal, the electrode touched by the black probe is the gate, while the remaining two electrodes are the drain and source, respectively. If the measured resistance values are both large, it suggests the reverse of the PN junction, meaning the reverse resistance, which can be judged as an N-channel FET, and the black probe is connected to the gate; if the resistance values are small, it indicates a forward PN junction, i.e., forward resistance, which determines it to be a P-channel field-effect transistor, and the black probe is also a gate. If the above situation does not occur, you can exchange the black and red probes as described above until the gate is identified.
Next, determine the quality of the FET using the resistance method. The resistance measurement method involves using a multimeter to measure the resistance between the source and drain, gate and source, gate and drain, and between the two gates G1 and G2. Whether these measurements are consistent helps determine the quality of the tube. Specifically, first place the multimeter in the R×10 or R×100 scale, and measure the resistance between the source S and the drain D. Usually, this resistance falls within the range of tens of ohms to several thousand ohms (different models may vary). If the measured resistance is greater than the normal value, it might indicate poor internal contact; if the measured resistance is infinite, it could be an internal fault. Then, switch the multimeter to the R×10k scale and measure the resistance between the gate G1 and G2, gate and source, and gate and drain. If the resistance values are infinite, it indicates the tube is normal; if these resistance values are too small or are conductive paths, the tube is faulty. Note that if the two gates are broken in the tube, the component substitution method can be used for testing.
Additionally, estimate the amplification capability of the FET using the inductive signal input method. The specific method involves using the R×100 scale of the multimeter resistance, connecting the red probe to the source S, and the black probe to the drain D, while adding a power supply voltage of 1.5V to the FET. At this point, the needle indicates the resistance between the drain and source. Next, pinch the gate G of the junction field-effect transistor by hand to apply the induced voltage signal from the body to the gate. Due to the amplification effect of the tube, the drain-source voltage VDS and the drain current ID both change, resulting in a change in the resistance between the drain and source, and thus the needle exhibits a large amplitude swing. If the needle swings minimally when the gate is pinched by hand, the tube’s amplification capability is poor; a large swing indicates strong amplification capability; if the needle does not move, the tube is faulty.
Based on the aforementioned method, we used the R×100 scale of the multimeter to measure the junction field-effect transistor 3DJ2F. Initially, the G pole was opened, and the drain-source resistance RDS was measured at 600Ω. After pinching the G pole, the needle swung significantly to the left, indicating an RDS of 12kΩ. The large amplitude swing of the needle suggested that the tube was in good condition and had a larger amplification factor.
When using this method, note the following: First, when testing a field-effect tube, the multimeter needle may swing to the right (resistance decreases) or to the left (resistance increases). This occurs because the AC voltage induced by the human body is higher, and the operating points of different FETs measured by the resistance scale may vary (or they may work in the saturation region or unsaturated region). Tests show that the RDS of most tubes increases, i.e., the needle swings to the left; the RDS of a few tubes decreases, causing the needle to swing to the right. However, regardless of the direction of the needle's swing, as long as the swing is large, the tube has a significant amplification capability. Second, this method also applies to MOS FETs. However, note that the input resistance of the MOS FET is high, so the induced voltage on the gate G should not be too high. Do not pinch the gate directly by hand; instead, use an insulated-handle screwdriver with a metal rod to touch the gate to prevent the body’s induced charge from being directly applied to the gate, which could cause gate breakdown. Third, after each measurement, the GS should be short-circuited. This is because the GS junction capacitance will charge with a small amount of charge, establishing the VGS voltage, so the needle may not move when remeasuring, and only releasing the GS interelectrode charge short circuit allows movement.
To discriminate unmarked FETs using the resistance method, first find two resistors with a resistance value, i.e., the source S and the drain D, by measuring the resistance, and the remaining two legs are the first gate G1 and the second gate G2. Record the resistance value between the source S and the drain D measured by the two probes, measure again, record the measured resistance value, and measure the resistance twice. The black probe-connected electrode is the drain D; the red probe is connected to the source S. The S and D poles identified by this method can also be verified by the method of estimating the amplification capability of the tube, i.e., the black probe with large amplification capability is connected to the D pole; the red probe is grounded, and the two test results should be the same. After determining the positions of the drain D and the source S, install the circuit according to the corresponding positions of D and S. Generally, G1 and G2 are also aligned sequentially, determining the positions of the two gates G1 and G2. Thus, the order of the D, S, G1, and G2 pins is determined.
To judge the size of the transconductance by measuring the change in the reverse resistance value, when measuring the transconductance performance of the VMOS N-channel enhancement type FET, the red S-table can be used to connect the source S and the black probe to the drain D, which is equivalent to adding a reverse voltage between the source and drain. At this time, the gate is open, and the reverse resistance of the tube is very unstable. Select the ohmic scale of the multimeter in the high resistance of R×10kΩ, and the voltage in the meter is high. When the gate G is touched by hand, the reverse resistance value of the tube changes significantly. The larger the change, the higher the transconductance value of the tube. If the transconductance of the tube is small, use this method to measure the reverse resistance, which does not change much.
Second, the use of FETs:
(1) To safely use the FET, the dissipated power limit, the maximum drain-source voltage, the maximum gate-source voltage, and the maximum current cannot be exceeded in the circuit design.
(2) When using FETs of all types, the required bias in the circuit must be strictly followed, and the polarity of the FET bias should be observed. For example, the junction between the source and gate of the junction field-effect transistor is a PN junction; the gate of the N-channel transistor cannot be positively biased; the gate of the P-channel transistor cannot be negatively biased, and so on.
(3) Due to the extremely high input impedance of the MOS FET, the pins must be short-circuited during transportation and storage. Metal shielded packaging should be used to prevent external induced potentials from penetrating the gate. In particular, it should be noted that the MOS FET cannot be placed in a plastic box. It is best to store it in a metal box, and also pay attention to the moisture resistance of the tube.
(4) To prevent the gate breakdown of the FET, it is required that all test instruments, workbenches, soldering irons, and the circuit itself must have good grounding; when the pins are soldered, the source is soldered first; before connecting to the circuit, all the lead ends of the tube should be kept short-circuited with each other, and the short-circuit material is removed after soldering; when removing the tube from the component holder, the grounding of the human body should be ensured in an appropriate manner; if, of course, the use of advanced gas-fired soldering irons makes soldering FETs more convenient and safe; it is absolutely not possible to plug or unplug tubes from the circuit when the power supply is not turned off. These safety measures must be considered when using FETs.
(5) When installing the FET, pay attention to the installation location to avoid heating elements; to prevent the vibration of the tube, it is necessary to fasten the tube casing; when bending the pins, it should be larger than the root size by 5 mm to prevent bending of the pins and causing air leaks.
For power FETs, there must be good heat dissipation conditions. Since the power FET is used under high load conditions, it is necessary to design a sufficient heat sink to ensure that the temperature of the housing does not exceed the rated value, so that the device can work stably and reliably for a long time.
In short, to ensure the safe use of FETs, there are many things to be aware of, and the safety measures adopted are various. Professional and technical personnel, especially the majority of electronic enthusiasts, must take practical measures based on their actual conditions to use FETs safely and effectively.
Third, VMOS FET
The VMOS field-effect transistor (VMOSFET), also known as the VMOS tube or power FET, is called the V-channel MOS field-effect transistor. It is a new high-efficiency, power-switching device developed after the MOSFET. It not only inherits the high input impedance of the MOS FET (≥108W), the drive current is small (about 0.1μA), but also has high withstand voltage (up to 1200V), large operating current (1.5A~100A), and high output power (1~250W), as well as excellent characteristics such as the linearity of transconductance, fast switching speed, etc. It is due to the combination of the advantages of the tube and the power transistor that it is widely used in voltage amplifiers (voltage amplification up to several thousand times), power amplifiers, switching power supplies, and inverters.
The VMOS field-effect power tube has the advantages of extremely high input impedance and a large linear amplification area, especially its negative current temperature coefficient, i.e., the on current will rise and decrease with the tube temperature when the gate-source voltage is constant. This eliminates the possibility of tube damage caused by the "secondary breakdown" phenomenon. Therefore, the parallel connection of VMOS tubes is widely used.
It is well known that the gate, source, and drain of a conventional MOS FET are substantially on the same level of the chip, and the operating current flows substantially in the horizontal direction. The VMOS tube is different. As can be seen from Figure 1, its two major structural features: first, the metal gate uses a V-groove structure; second, it has vertical conductivity. Since the drain is drawn from the back side of the chip, the ID does not flow horizontally along the chip, but starts from the heavily doped N+ region (source S), flows into the lightly doped N-drift region through the P channel, and finally reaches vertically downward. Drain D. The current direction is as indicated by the arrow in the figure, and since the flow cross-sectional area is increased, a large current can be passed. Since there is a silicon dioxide insulating layer between the gate and the chip, it still belongs to the insulated gate type MOS field-effect transistor.
The main domestic manufacturers of VMOS FETs are factories 877, Tianjin Semiconductor Device 4, Hangzhou Electronic Tube Factory, etc. Typical products include VN401, VN672, VMPT2, etc.
The following describes how to detect VMOS tubes:
1. Determine the gate G
Set the multimeter to R×1k to measure the resistance between the three pins. If the resistance of a foot and its two feet is found to be infinite and remains infinite after exchanging the probes, it proves that this pin is the G pole because it is insulated from the other two pins.
2. Determine source S and drain D
As shown in Figure 1, there is a PN junction between the source and the drain, so the S pole and the D pole can be identified according to the difference in the positive and negative resistances of the PN junction. The resistance is measured twice by the exchange probe method, where the resistance value is low (generally several thousand ohms to ten thousand ohms), and the first time is the forward resistance. At this time, the black probe is the S pole, and the red probe is connected to the D pole.
3. Measure the drain-source on-state resistance RDS(on)
Short-circuit the GS pole, select the R×1 file of the multimeter, connect the black probe to the S pole, and connect the red probe to the D pole, and the resistance value should be several ohms to ten ohms.
Due to different test conditions, the measured RDS(on) value is higher than the typical values given in the manual. For example, an IRFPC50 VMOS tube is measured with a 500-type multimeter R×1 file, and RDS(on)=3.2Ω, which is greater than 0.58Ω (typical).
4. Check the transconductance
Place the multimeter in the R×1k (or R×100) file, connect the red probe to the S pole, the black probe to the D pole, and use a hand screwdriver to touch the grid. The needle should have obvious deflection. The larger the deflection, the higher the transconductance of the tube.
Precautions:
(1) VMOS tubes are also divided into N-channel tubes and P-channel tubes, but most products belong to N-channel tubes. For P-channel tubes, the position of the test leads should be exchanged during measurement.
(2) A few VMOS tubes have protection diodes between the GS. Items 1 and 2 of this test method are no longer applicable.
(3) There is also a VMOS tube power module on the market, which is specifically used for AC motor controllers and inverters. For example, the IRFT001 module produced by IR Company of the United States has three N-channel and one P-channel tube inside to form a three-phase bridge structure.
(4) Now the commercially available VNF series (N-channel) products are UHF power FETs produced by Supertex Corporation of the United States. The highest operating frequency is fp=120MHz, IDSM=1A, PDM=30W, common source small signal low frequency transconductance gm=2000μS. They are suitable for high-speed switching circuits and broadcasting and communication equipment.
(5) After using a VMOS tube, a suitable heat sink must be added. Taking VNF306 as an example, the maximum power can reach 30W after the tube is equipped with a 140×140×4 (mm) heat sink.
(6) After the multiple tubes are connected in parallel, the high-frequency characteristics of the amplifier are deteriorated due to the corresponding increase in the inter-electrode capacitance and the distributed capacitance, and the high-frequency parasitic oscillation of the amplifier is easily caused by the feedback. For this reason, the parallel composite tube tubes generally do not exceed four, and an anti-parasitic oscillation resistor is connected in series to the base or the gate of each tube.